View LP61L1024-15_8550269.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lp61l1024 128k x 8 bit 3.3v high speed low vcc cmos sram (august, 2004, version 2.2) amic technology, corp. document title 128k x 8 bit 3.3v high speed low vcc cmos sram revision history rev. no. history issue date remark 2.0 add product family and 32-pin tssop package may 9, 2002 final 2.1 add 36 ball bga package type august 22, 2002 2.2 add pb-free package type august 9, 2004
lp61l1024 128k x 8 bit 3.3v high speed low vcc cmos sram (august, 2004, version 2.2) 1 amic technology, corp. features general description ? single +3.3v power supply ? access times: 12/15 ns (max.) ? current: operating: 170ma (max.) standby: 10ma (max.) ? full static operation, no cl ock or refreshing required ? all inputs and outputs are di rectly ttl compatible ? common i/o using three-state output ? output enable and two chip enable inputs for easy application ? data retention voltage: 2.0v (min.) ? available in 32-pin soj 300 mil, 32-pin tsop and 32-pin tssop and 36-pin csp packages the lp61l1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3v power supply. inputs and three-stat e outputs are ttl compatible and allow for direct interfacing with common system bus structures. two chip enable inputs are provided for power-down and device enable and an output enable input is included for easy interfacing. data retention is guaranteed at a power supply voltage as low as 2.0v. product family power dissipation product family operating temperature vcc range speed data retention (i ccdr , typ.) standby (i sb1 , typ.) operating (i cc1 , typ.) package type lp61l1024 0 c ~ 70 c 3v ~ 3.6v 12/15 ns 0.4ma 0.5ma 130ma 32l soj 32l tsop 32l tssop 36b bga 1. typical values are measured at vcc = 3.0v, t a = 25 c and not 100% tested. 2. data retention current vcc = 2.0v.
lp61l1024 (august, 2004, version 2.2) 2 amic technology, corp. pin configurations ? soj ? tsop / tssop ? csp (chip size package) 36-pin top view block diagram vcc gnd decoder 256 x 4096 memory array input data circuit column i/o control circuit a0 a14 a15 a16 i/o 1 i/o 8 ce2 ce1 oe we pin description pin no. symbol description 2 - 12, 23, 25 - 28, 31 a0 - a16 address inputs 29 we write enable 24 oe output enable 22 ce1 chip enable 30 ce2 chip enable 1 nc no connection 13 - 15, 17 - 21 i/o 1 - i/o 8 data input/outputs 32 vcc power supply 16 gnd ground nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o 1 i/o 2 i/o 3 i/o 4 gnd i/o 5 i/o 6 i/o 7 i/o 8 ce1 a10 oe a9 a8 a13 we ce2 a15 vcc a11 lp61l1024s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 lp61l1024v(x) 1 16 17 32 pin no. pin name pin no. pin name 12 a9 34567891011121314 30 29 28 27 26 25 24 22 19 21 20 23 18 17 a8 a13 ce2 a15 vcc nc i/o 8 a16 a14 a12 a7 a6 a3 a2 a1 a0 i/o 1 i/o 2 gnd i/o 4 i/o 5 i/o 6 i/o 7 i/o 3 a11 we ce1 15 16 31 32 a5 a4 a10 oe a0 i/o 4 i/o 5 gnd vcc i/o 6 i/o 7 a9 a10 oe a11 ce1 a12 a13 a14 a16 nc nc a15 i/o 3 i/o 2 i/o 1 i/o 0 gnd vcc a1 a2 nc we nc a5 a4 a3 a6 a7 a8 6 5 4 3 2 1 a b c d e f g h
lp61l1024 (august, 2004, version 2.2) 3 amic technology, corp. recommended dc operating conditions (t a = 0 c to + 70 c) symbol parameter min. typ. max. unit vcc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.2 - vcc + 0.3 v v il input low voltage -0.3 0 +0.8 v c l output load - - 30 pf ttl output load - - 1 - absolute maximum ratings* vcc to gn d ...............................................-0.5v to +7.0v in, in/out volt to gn d..................... -0.5v to vcc +0.5v operating temperature, topr .......................0 c to +70 c storage temperatur e, tstg..................... -55 c to +125 c temperature under bias, tbias................ -10 c to +85 c power dissipati on, pt................................................ 1.0w soldering temp . & time ............................. 260 c, 10 sec *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (t a = 0 c to + 70 c, vcc = 3.3v + 10%, gnd = 0v) symbol parameter lp61l1024-12/15 unit conditions min. max. ? i li ? input leakage current - 2 a v in = gnd to vcc ? i lo ? output leakage current - 2 a ce1 = v ih or ce2 = v il or oe = v ih or we = v il v i/o = gnd to vcc i cc1 (1) dynamic operating current - 170 ma ce1 = v il , ce2 = v ih i i/o = 0 ma i sb - 30 ma ce1 = v ih or ce2 = v il i sb1 standby power supply current - 10 ma ce1 vcc - 0.2v, ce2 vcc - 0.2v, v in 0.2v or v in vcc - 0.2v i sb2 - 10 ma ce1 0.2v, ce2 0.2v v in 0.2v or v in vcc - 0.2v v ol output low voltage - 0.4 v i ol = 8 ma v oh output high voltage 2.4 - v i oh = -4 ma note: 1. i cc1 is dependent on output loading, cycle rates, and read/write patterns
lp61l1024 (august, 2004, version 2.2) 4 amic technology, corp. truth table mode ce1 ce2 oe we i/o operation supply current standby h x x x high z i sb , i sb1 x l x x high z i sb , i sb2 output disable l h h h high z i cc1 read l h l h d out i cc1 write l h x l d in i cc1 note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance 8 pf v in = 0v c i/o * input/output capacitance 10 pf v i/o = 0v * these parameters are sampled and not 100% tested. ac characteristics (t a = 0 c to +70 c, vcc = 3.3v + 10, gnd = 0v) symbol parameter lp61l1024-12 LP61L1024-15 unit min. max. min. max. read cycle t rc read cycle time 12 - 15 - ns t aa address access time - 12 - 15 ns t ace1 chip enable access time ce1 - 12 - 15 ns t ace2 ce2 - 12 - 15 ns t oe output enable to output valid - 7 - 9 ns t clz1 chip enable to output in low z ce1 3 - 5 - ns t clz2 ce2 3 - 5 - ns t olz output enable to output in low z 2 - 2 - ns t chz1 chip disable to output in high z ce1 - 7 - 10 ns t chz2 ce2 - 7 - 10 ns t ohz output disable to output in high z 2 7 2 9 ns t oh output hold from address change 3 - 5 - ns
lp61l1024 (august, 2004, version 2.2) 5 amic technology, corp. ac characteristics (continued) symbol parameter lp61l1024-12 LP61L1024-15 unit min. max. min. max. write cycle t wc write cycle time 12 - 15 - ns t cw chip enable to end of write 10 - 12 - ns t as address setup time of write 0 - 0 - ns t aw address valid to end of write 10 - 12 - ns t wp write pulse width 8 - 10 - ns t wr write recovery time 0 - 0 - ns t whz write to output in high z 0 7 0 8 ns t dw data to write time overlap 8 - 10 - ns t dh data hold from write time 0 - 0 - ns t ow output active from end of write 5 - 5 - ns notes: t chz1 , t chz2 , t ohz , and t whz are defined as the time at which the out puts achieve the open circuit condition and are not referred to output voltage levels. timing waveforms read cycle 1 (1, 2, 4) t rc t oh t aa t oh address d out
lp61l1024 (august, 2004, version 2.2) 6 amic technology, corp. read cycle 2 (1, 3, 4, 6) t clz1 5 t ace1 t chz1 5 ce1 d out read cycle 3 (1, 4, 7, 8) t clz2 5 t ace2 t chz2 5 ce2 d out read cycle 4 (1) t rc address oe t aa t oe t olz 5 t ace1 t clz2 5 t ace2 t clz2 5 t chz2 5 t ohz 5 t chz1 5 t oh ce1 ce2 d out notes: 1. we is high for read cycle. 2. device is continuously enabled ce1 = v il and ce2 = v ih . 3. address valid prior to or coincident with ce1 transition low. 4. oe = v il . 5. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested. 6. ce2 is high. 7. ce1 is low. 8. address valid prior to or coincident with ce2 transition high.
lp61l1024 (august, 2004, version 2.2) 7 amic technology, corp. timing waveforms (continued) write cycle 1 (6) (write enable controlled) t wc address ce1 ce2 d in t ow t dh t dw t whz t wp 2 t as 1 (4) (4) t cw 5 t aw t wr 3 we d out write cycle 2 (chip enable controlled) t wc address ce1 ce2 d in t dh t dw (4) (4) t cw 5 t aw t wr 3 we d out t whz 7 t wp 2 t cw 5 t as 1 notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp ) of a low ce1, a high ce2 and a low we . 3. t wr is measured from the earliest of ce1 or we going high or ce2 going low to the end of the write cycle. 4. if the ce1 low transition or the ce2 high transition occurs simultaneously with the we low transition or after the we transition, outputs remain in a high impedance state. 5. t cw is measured from the later of ce going low or ce2 going high to the end of write. 6. oe is continuously low. ( oe = v il ) 7. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested.
lp61l1024 (august, 2004, version 2.2) 8 amic technology, corp. ac test conditions input pulse levels 0v to 3.0v input rise and fall time 3 ns input and output timing reference levels 1.5v output load see figures 1 and 2 +3.3v i/o 350? 320? 30pf* * including scope and jig. +3.3v i/o 350? 320? 5pf* * including scope and jig. figure 1. output load figure 2. output load for t clz1 , t clz2 , t ohz , t olz , t chz1 , t chz2 , t whz , and t ow data retention characteristics (t a = 0 c to 70 c) symbol parameter min. max. unit conditions v dr1 vcc for data retention 2 3.6 v ce1 vcc - 0.2v ce2 vcc - 0.2v or ce2 0.2v v dr2 2 3.6 v ce2 0.2v ce1 vcc - 0.2v or ce1 0.2v i ccdr1 data retention current - 5 ma vcc = 3.0v ce1 vcc - 0.2v ce2 vcc - 0.2v v in vcc - 0.2v or v in 0.2v i ccdr2 - 5 ma vcc = 3.0v ce2 0.2v ce1 0.2v v in vcc - 0.2v or v in 0.2v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recovery time 5 - ms
lp61l1024 (august, 2004, version 2.2) 9 amic technology, corp. low vcc data retention waveform (1) ( ce1 controlled) vcc ce1 t cdr v ih 3.0v t r v ih 3.0v data retention mode v dr 2v ce1 v dr - 0.2v low vcc data retention waveform (2) (ce2 controlled) vcc ce2 t cdr v il 3.0v t r v il 3.0v data retention mode v dr 2v ce2 0.2v ordering information part no. access time (ns) operating current max. (ma) standby current max. (ma) package lp61l1024s-12 32l soj (300 mil) lp61l1024s-12f 32l pb-free soj (300 mil) lp61l1024v-12 32l tsop lp61l1024v-12f 32l pb-free tsop lp61l1024x-12 32l tssop lp61l1024x-12f 32l pb-free tssop lp61l1024u-12 36l csp lp61l1024u-12f 12 170 10 36l pb-free csp lp61l1024s-15 32l soj (300 mil) lp61l1024s-15f 32l pb-free soj (300 mil) lp61l1024v-15 32l tsop lp61l1024v-15f 32l pb-free tsop lp61l1024x-15 32l tssop lp61l1024x-15f 32l pb-free tssop lp61l1024u-15 36l csp lp61l1024u-15f 15 170 10 36l pb-free csp
lp61l1024 (august, 2004, version 2.2) 10 amic technology, corp. package information soj 32/32ld (300mil body) outline dimensions unit: inches/mm 1 e min 0.026" a 2 e e 1 16 17 32 s seating plane d 0.004 a 1 b 1 b d y y y detail "a" h e a detail "a" b c section f-f base metal with plating f f symbol dimensions in inches dimensions in mm min. nom. max. min. nom. max. a 0128 0.132 0.140 3.25 3.35 3.56 a 1 0.052 - - 2.08 - - a 2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.020 0.41 0.46 0.51 b 1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.006 0.008 0.012 0.15 0.20 0.30 d 0.820 0.825 0.830 20.83 20.96 21.08 h e 0.330 0.335 0.340 8.39 8.51 8.63 e 0.295 0.300 0.305 7.49 7.62 7.75 e 1 0.260 0.267 0.274 6.61 6.78 6.96 e - 0.050 - - 1.27 - s - - 0.048 - - 1.22 y - - 0.004 - - 0.10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e doesn't include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
lp61l1024 (august, 2004, version 2.2) 11 amic technology, corp. package information tsop 32l type i (8 x 20mm) outline dimensions unit: inches/mm e l e l gauge plane a a 2 c 0.25 bsc detail "a" d y detail "a" s a 1 b h d d e 0.10(0.004) m 12.0 symbol dimensions in inches dimensions in mm a 0.047 max. 1.20 max. a 1 0.0040.002 0.100.05 a 2 0.0390.002 1.000.05 b 0.0080.001 0.200.03 c 0.0060.001 0.150.02 d 0.7240.004 18.400.10 e 0.3150.004 8.000.10 e 0.020 typ. 0.50 typ. h d 0.7870.007 20.000.20 l 0.0200.004 0.500.10 l e 0.031 typ. 0.80 typ. s 0.0167 typ. 0.425 typ. y 0.004 max. 0.10 max. 0 ~ 6 0 ~ 6 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash.
lp61l1024 (august, 2004, version 2.2) 12 amic technology, corp. package information tssop 32l type i (8 x 13.4mm) outline dimensions unit: inches/mm e detail "a" d 0.076mm detail "a" s b d 1 e d l e l a a 2 c a 1 seating plane dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.049 - - 1.25 a 1 0.002 - - 0.05 - - a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.0056 0.0059 0.0062 0.142 0.150 0.158 e 0.311 0.315 0.319 7.90 8.00 8.10 e 0.020 typ 0.50 typ d 0.520 0.528 0.535 13.20 13.40 13.60 d 1 0.461 0.465 0.469 11.70 11.80 11.90 l 0.012 0.020 0.028 0.30 0.50 0.70 l e 0.0275 0.0315 0.0355 0.700 0.800 0.900 s 0.0109 typ 0.278 typ 0 3 5 0 3 5 notes: 1. the maximum value of dimension d 1 includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
lp61l1024 (august, 2004, version 2.2) 13 amic technology, corp. package information 36ld csp (6 x 8 mm) outline dimensions unit: mm a 1 a 2 a b c d e f g h top view ball#a1 corner side view c seating plane // 0.25 c a (0.36) a b c d e f g h 123456 1 2 3 4 5 6 c 0.10 c s 0.25 s a b b (36x) bottom view ball*a1 corner e e 1 e b e d 1 d a 0.20(4x) 0.10 c dimensions in mm symbol min. nom. max. a 1.00 1.10 1.20 a 1 0.16 0.21 0.26 a 2 0.48 0.53 0.58 d 5.80 6.00 6.20 e 7.80 8.00 8.20 d 1 --- 3.75 --- e 1 --- 5.25 --- e --- 0.75 --- b 0.25 0.30 0.35 note: 1. the ball diameter, ball pitch, stand-off & package thickness are different from jedec spec mo192 (low profile bga family). 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 3. dimension b is measured at the maximum. 4. theere shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge.

▲Up To Search▲

Price & Availability of LP61L1024-15

	To Download LP61L1024-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .